1. Field of the Invention
The present invention relates to a reading circuit and a semiconductor memory device including the reading circuit.
2. Description of the Related Art
Conventionally, various types of electrically rewritable nonvolatile memories have been proposed including, for example, EEPROM (Electrically Erasable and Programmable Read Only Memory), flash EEPROM (hereinafter, also referred to as a “flash memory”), MRAM (Magnetic Random Access Memory), and OUM (Ovonic Unified Memory).
These types of nonvolatile memories are common in storing data in a memory cell and reading data from the memory cell, but have different structures.
For example, a flash memory uses, as a memory cell, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor; hereinafter, also referred to as a “transistor”) having a floating gate. In the flash memory, charge is accumulated in the floating gate of the memory cell. In accordance with the amount of charges accumulated in the floating gate, the threshold voltage of the gate electrode of the transistor changes. When a voltage equal to or greater than the threshold voltage is applied to the gate electrode of the transistor, a current flows through the transistor. In this specification, the threshold voltage of the gate electrode of the transistor will be referred to as the “threshold voltage of the transistor” or as the “threshold voltage”.
In general, the amount of charge accumulated in the floating gate is associated with data, and thus the threshold voltage of the transistor is associated with the data.
For reading data from a flash memory, a memory cell is selected from a plurality of memory cells through a word line and a bit line, and a prescribed voltage is applied to a drain electrode of the selected memory cell through the bit line. Then, the level of current flowing through the memory cell is changed depending on whether the applied voltage is higher or lower than the threshold voltage. Ideally, when the applied voltage is lower than the threshold voltage, no current flows through the memory cell. Therefore, data stored in the memory cell can be read as information by sensing, using a sense amplifier or the like, the change in the level of current flowing through the memory cell in accordance with the threshold voltage, more specifically, the change in the level of current flowing in the bit line connected to the memory cell.
An MRAM has a different structure from that of the flash memory. An MRAM having a combination of a TMR (Tunnel Magnetoresistance) element and a transistor has been proposed, for example.
In the case of an MRAM, data is read from a memory cell in substantially the same manner as in the flash memory. Specifically, a prescribed voltage is applied to a bit line connected to a memory cell, and the change in the level of current flowing through the bit line is sensed by a sense amplifier or the like.
For a circuit for sensing the change in the level of current flowing through a memory cell, it is desired to reduce the degree of change in the level of current flowing through the memory cell and to sense the change in the current level quickly in order to improve the performance of the memory cell.
FIG. 21 is a circuit diagram illustrating a conventional reading circuit 100.
The reading circuit 100 for reading information from a memory cell includes a bit line selecting transistor 102 for selecting a prescribed memory cell from a memory cell array 101 having a plurality of memory cells, a feedback bias circuit 103 connected to the bit line selecting transistor 102, a current supply circuit 115 connected to the feedback bias circuit 103, and a comparator circuit 105. The current supply circuit 115 includes a load circuit 104. The plurality of memory cells in the memory cell array 101 are each connected to a word line WL and a bit line BL.
The comparator circuit 105 has a first input terminal 113, a second input terminal 107, and an output terminal 108. The first input terminal 113 is connected to a connection point (anode 106) for connecting the current supply circuit 115 and the feedback bias circuit 103. The second input terminal 107 is supplied with a reference voltage. The comparator circuit 105 compares the potential of the node 106 connected to the first input terminal 113 with the potential of the reference voltage supplied from the second input terminal 107, and outputs the result of the comparison as information from the output terminal 108.
The reading circuit 100 having the above-described structure operates as follows.
Each of the plurality of memory cells included in the memory cell array 101 is a flash memory cell. A memory cell from which data is to be read is selected from the plurality of memory cells by a word line and a bit line. In the following description, the memory cell from which data is to be read will be referred to as the “reading memory cell”.
The potential of the bit line is at the ground level before the reading memory cell is selected from the plurality of memory cells.
First, a word line connected to the reading memory cell is selected, and a bit line connected to the reading memory cell is selected by the bit line selecting transistor 102.
Next, the current supply circuit 115 starts charging the bit line. When the bit line is charged to a certain level, the feedback bias circuit 103 clamps the potential of the bit line. Then, the potential of the node 106 is determined based on how the potential of the bit line is changed after once being clamped in accordance with the level of current flowing through the reading memory cell and the current supply capability of the current supply circuit 115.
Specifically, when the potential of the bit line is raised to a certain level, the potential which is output from an inverter circuit included in the feedback bias circuit 103 connected to the bit line is inverted. Thus, the feedback bias circuit 103 electrically disconnects the reading memory cell and the comparator circuit 105 from each other. In the case where the reading memory cell has a high threshold voltage and thus no current flows through the reading memory cell, the feedback bias circuit 103 keeps the reading memory cell and the comparator circuit 105 disconnected from each other. In the case where the reading memory cell has a low threshold voltage and thus a current flows through the reading memory cell, the output from the inverter of the feedback bias circuit 103 is again inverted, thereby electrically connecting the reading memory cell and the comparator circuit 105. As a result, the potential of the node 106 which is supplied with the current by the current supply circuit 115 is changed in accordance with the threshold voltage of the reading memory cell.
While the current supply capability of the current supply circuit 115 is kept the same, the potential of the first input terminal 113 of the comparator circuit 105 is changed in accordance with the level of current flowing through the reading memory cell. When the reading memory cell is a flash memory cell as in this example, the level of current flowing through the reading memory cell is changed in accordance with the threshold voltage of the transistor of the reading memory cell. Accordingly, the potential of the node 106 is changed in accordance with the threshold voltage of the transistor of the reading memory cell.
The reference voltage of the second input terminal 107 of the comparator circuit 105 (hereinafter, referred to as a “REF voltage”) is set to a level at which the change in the potential of the node 106 can be found by the comparator circuit 105.
For example, a voltage intermediate between the potential of the node 106 when the threshold voltage of the transistor of the reading memory cell is high and the potential of the node 106 when the threshold voltage of the transistor of the reading memory cell is low is set as the REF voltage.
With such a setting, the comparator circuit 105 compares the potential of the REF voltage and the potential of the node 106 so as to determine the threshold voltage of the transistor of the reading memory cell and thus read data stored in the reading memory cell.
It is not advantageous to excessively increase the current supply capability of the current supply circuit 115, since when the current supply capability is excessively large as compared to the level of current flowing through the bit line, the potential of the node 106 is not favorable for the reading operation for the following reasons.
As described above, the potential of the node 106 depends on the threshold voltage of the transistor of the reading memory cell. When the bit line selecting transistor 102 becomes conductive and a current flows through the bit line, the potential of the node 106 is changed in accordance with the threshold voltage of the transistor of the reading memory cell. The degree of change in the potential of the node 106 increases as the current supply capability of the current supply circuit 115 increases. The reason is that as the current supply capability of the current supply circuit 115 is higher, the level of current flowing through the bit line is also higher. Accordingly, when the current supply capability of the current supply circuit 115 is excessively high, a long time is required for the potential of the bit line to reach a value appropriate to read data from the reading memory cell, which extends the time for reading data from the reading memory cell. Especially when the capacitance of the bit line is large, the reading time of data is excessively long.
In order to increase the capacity of, and reduce the production cost of, a semiconductor memory device including the reading circuit 100, it has been demanded to reduce the size of the circuits. For this purpose, dielectric layers of the circuits are being made thinner and thinner. In accordance with this, the capacity of bit lines are becoming larger and larger. Therefore, a reading circuit for reading data at high speed from memory cells even with large capacitance bit lines is demanded.
In order to realize such a reading circuit, Japanese Laid-Open Publication No. 2000-311493 proposes a reading circuit having a charge circuit for charging a bit line (hereinafter, referred to as a “precharge circuit”).
FIG. 22 is a circuit configuration illustrating a reading circuit 100A disclosed by Japanese Laid-Open Publication No. 2000-311493. In FIG. 22, elements identical to those in FIG. 21 bear identical reference numerals and descriptions thereof will be omitted. The elements having substantially the same functions as those in FIG. 21 bear corresponding reference numerals (for example, a feedback bias circuit 103A instead of the feedback bias circuit 103; and the current supply circuit 115A instead of the current supply circuit 115).
The reading circuit 100A includes a feedback bias circuit 103A, a current supply circuit 115A, a comparator circuit 105 and a precharge circuit 109 for charging a bit line. The current supply circuit 115A includes an n-channel transistor as a load circuit 104a. The precharge circuit 109 has a significantly larger current supply capability than that of the current supply circuit 115A.
An operation of the reading circuit 100A will be described.
First, a bit line connected to a reading memory cell is charged by the precharge circuit 109.
When the bit line is charged to a certain level, the charging by the precharge circuit 109 is stopped, and information is read from a reading memory cell by the comparator circuit 105, the current supply circuit 115A, and the feedback bias circuit 103A in accordance with the change in the level of current flowing through the reading memory cell.
In the reading circuit 100A, the precharge period in which the precharge circuit 109 charges a bit line is determined by an ATDP (address transition detection pulse) signal pulse. An ATDP signal is generated based on a signal by, for example, an address transition detection circuit (not shown).
A clamp potential represented by a clamp voltage, at which the potential of the bit line is clamped, is determined by the feedback bias circuit 103A.
In the reading circuit 100A, a sense amplification enable (SAE) signal becomes an L (low) level during an initial period of the reading operation. When the SAE signal is at the “L” level, the feedback bias circuit 103A stabilizes the potential of the bit line at a prescribed clamp voltage.
During the initial period of the reading operation, the ATDP signal, which corresponds to a bit line precharge signal, becomes the “L” level. In this case, the precharge circuit 109 charges the bit line at high speed.
Hereinafter, an operation of a transistor 110 of the feedback bias circuit 103A will be described.
A driving circuit 111 of the reading circuit 100A is set as follows: when the potential of a node 109N connected to an output terminal of the precharge circuit 109 is changed by a small degree in accordance with the current capability of a reading memory cell 101a while the bit line is charged to the clamp voltage, the output voltage of the driving circuit 111 of the feedback bias circuit 103A (i.e., the potential of a node 111N) is changed.
More specifically, when the potential of the node 111N (i.e., the potential of the gate voltage of the transistor 110) is changed, the ON resistance of the transistor 110 is changed. Thus, the ON resistance of the transistor 110 is changed depending on the potential of the node 109N. When the potential of the node 109N is low, the potential of the node 111N connected to the gate electrode of the transistor 110 is increased, and as a result, the ON resistance is decreased. When the potential of the node 109N is high, the potential of the node 111N connected to the gate electrode of the transistor 110 is decreased, and as a result, the ON resistance is increased.
As described above, the ON resistance of the transistor 110 is changed in accordance with the change in the potential of the node 109N (i.e., the change in the output voltage of the precharge circuit 109). In accordance with the change in the ON resistance of the transistor 110, a potential difference is generated at the first input terminal 113 of the comparator circuit 105.
A charging operation performed by the precharge circuit 109 will be described. In this example, the precharge circuit 109 charges the bit line connected to a reading memory cell 101a. 
When an ATDP signal is input, the precharge circuit 109 operates to charge the bit line at high speed.
It is assumed here that the precharge circuit 109 is stopped before the potential of the bit line reaches a desired level (i.e., the clamp potential which is determined by the feedback bias circuit 103A) in response to the ATDP signal. Then, the transistor 110, which is on the output side of the feedback bias circuit 103A is kept OFF regardless of the threshold voltage of the reading memory cell 101a, and the bit line is continuously charged slowly by the current supply circuit 115A until the bit line is charged to the desired level. Even when the level of current flowing through the reading memory cell 101a is changed, the potential of a node 106N does not significantly change.
The reason is as follows. When the potential of the bit line is lower than the potential of the clamp potential determined by the feedback bias circuit 103A, the potential of the node 111N in the feedback bias circuit 103A does not change regardless of the level of current flowing through the reading memory cell 101a. The potential of the node 111N which is in the feedback bias circuit 103A and is connected to the output terminal of the driving circuit 111 is set as follows: When the potential of the bit line becomes close to the potential of the clamp potential (i.e., the desired level), the potential of the node 111N is changed based on a small change in the potential of the node 109N which is caused by the level of current flowing through the node 109N connected to the output terminal of the precharge circuit 109.
In general, the clamp potential of the feedback bias circuit 103A is determined in various systems depending on the type of the reading memory cell 101a. Often, the clamp voltage represented by the clamp potential is determined to a level which is within a range in which data is not destroyed when being read from the reading memory cell 101a and further in which the level of current flowing through the bit line is as high as possible.
Therefore, when the potential of the bit line is lower than the potential of the clamp potential, the level of current flowing through the bit line is not changed as much as expected, and the feedback bias circuit 103A does not operate as expected. As a result, the potential of the first input terminal 113 of the comparator circuit 105 is not expected to undergo a large change.
When the potential of the node 106N does not greatly change for the reason that the level of current flowing through the bit line does not largely change, the comparison operation of the comparator circuit 105 becomes slow. This extends the reading time required for reading data from the reading memory cell 101a. For this reason, when the bit line is not sufficiently charged, the reading time is extended.
Next, the case where the precharge circuit 109 keeps on operating even after the potential of the bit line reaches the desired level (i.e., the clamp potential determined by the feedback bias circuit 103A) in response to the ATDP signal (namely, when a transistor 109a, which is on the output side of the precharge circuit 109 is kept ON) will be described.
In this case, the bit line is charged to the clamp potential set by the feedback bias circuit 103A. Even if the precharge circuit 109 is operated to charge more, the potential of the node 111N in the feedback bias circuit 103A is decreased and the transistor 109b of the precharge circuit 109 is turned OFF. As a result, the precharge circuit 109 stops the charging operation. The transistor 110 is also turned OFF, and thus the bit line is not charged. However, the node 106N is charged by the current supply circuit 115A. Therefore, there is a possibility that the node 106N may be charged up to the charging limit which is determined by the current supply circuit 115A. In this example, the potential of the node 106N may be raised to close to the level of the potential of the power supply VCC less the potential of the threshold voltage of an n-channel transistor 104a. 
As described above, the gate voltage of the transistor 110 of the feedback bias circuit 103A is changed and there is a voltage difference between the drain voltage and the source voltage of the transistor 110. Therefore, the potential of the node 106N is changed in accordance with the level of current flowing through the reading memory cell 101a after the charging of the bit line by the precharge circuit 109 is completed.
Even though there is a large potential difference of the node 106N, once the potential of the node 106N is raised to a certain level, the comparator circuit 105 connected to the node 106N does not operate at high speed unless the potential of the node 106N is decreased to the operating point of the comparator circuit 105. This means that time is wasted during the reading operation from the reading memory cell 101a. 
In the case where while the potential of the node 106N is increasing by charging, the precharge circuit 109 completes the charging operation in response to the ATDP signal, and further a desired level of current flows through the bit line, the potential of the node 106N stops increasing at the same time as the completion of the charging operation of the bit line. Then, the reading operation from the reading memory cell 101a is started.
However, the node 106N has a significantly shorter line than the bit line and thus can be charged in a very short time as compared to the entire bit line. Therefore, when the node 106N is charged in response to the ATDP signal even for a short time after the completion of the charging operation by the precharge circuit 109, the potential of the node 106N is increased.
Actual devices involve variances in the physical conditions of, for example, voltage, temperature and production process. It is practically very difficult to provide the optimum precharge pulse width for the ATDP signal.
In comprehensive consideration of these issues, the entire reading operation may be performed as follows in order to shorten the reading time from the reading memory cell 101a. 
Specifically, it is preferable to set the pulse width of the precharge period such that the node 106N is charged to raise the potential thereof until the bit line is completely charged rather than leaving the bit line insufficiently charged. In this case, after the charging operation is completed and the potential of the node 106N is decreased to the operating point of the comparator circuit 105, the reading operation is performed.
In this case also, time is wasted until the potential of the node 106N is decreased to the operating point of the comparator circuit 105.
The level of current flowing through the bit line is closely related to the operation of selecting a word line WL.
For example, when the reading memory cell 101a is a flash memory cell, unless the potential of the word line reaches the intended level, the gate voltage of the transistor of the reading memory cell 101a is low. As a result, the level of current flowing through the bit line is also low.
In the case where the level of current supplied from the current supply circuit 115A does not rely on the potential of the bit line and thus does not change, and further the level of current flowing through the bit line is low, a long time is necessary for the potential of the bit line to reach the intended level and for a sufficient level of current to flow through the bit line. This also extends the reading time from the reading memory cell 101a. 
The selection of the word line WL and the charging of the bit line BL are often performed in parallel in order to shorten the reading time from a reading memory cell. When the selection of the word line is suspended in the middle (specifically, when the potential of the word line does not reach the intended level and the bit line is charged to the desired clamp potential), the level of current flowing through the bit line is lower than that when the potential of the word line reaches the intended level. Therefore, the current supply capability of the current supply circuit 115A is high with respect to the bit line, and the potential of the node 106N is raised in accelerating manner. The potential of the node 106N is increased in a short time.
Hereinafter, the case where the precharge circuit 109 is controlled by the potential of the node 111N which is on the output side of the feedback bias circuit 103A, i.e., which is connected to the gate electrode of the transistor 110, will be described.
The node 111N is originally provided to determine the clamp potential of the selected bit line, and therefore the potential of the node 111N is changed in accordance with even a small change in the potential of the node 109N in the vicinity of the clamp potential.
However, the potential of the node 111N cannot be used for controlling the precharge circuit 109 for the following reason. The potential of the bit line is close to the clamp potential and the bit line is almost completely charged. Therefore, the precharge circuit 109 has almost no current supply capability, and the bit line is not charged to a level higher than the clamp potential which is set by the feedback bias circuit 103A.
As described above, even in the case where the clamp potential of the bit line is set by the feedback bias circuit 103A and is rapidly charged by the precharge circuit 109, it is very difficult to shorten the reading time.